ASIC Physical Design
End-to-end backend implementation from synthesized netlist to GDSII across 180 nm to 12 nm: floorplanning, placement, CTS, routing and physical optimization.
Physical Design · STA · Fault tolerance
Rafael Oliveira
Physical Design & STA Engineer taking silicon from netlist to GDSII, and researching how to keep it reliable.
01 / About
Physical design engineer & researcher
Microelectronics and nanotechnology since 2018.
I implement ASICs end to end, from synthesized netlist to signoff-clean GDSII, with a focus on timing-driven design closure.
I hold a B.Sc. in Computer Science from the Federal University of Santa Catarina (UFSC), where I am also completing my M.Sc. My research targets the mitigation of process variability and radiation-induced failures in combinational circuits, and I work on radiation-hardened standard cell libraries and low-power RISC-V ASICs.
I have hands-on experience across the full RTL-to-GDSII flow with industry-standard EDA tools, in nodes from 180 nm down to 12 nm, and have published in international journals and conferences on digital design and fault tolerance.
I founded OSIRIS, a research group on RISC-V microarchitecture, and created VLSI Brasil, a blog sharing semiconductor knowledge in Portuguese.
7peer-reviewed publications
2018doing VLSI research since
180→7nm, technology nodes worked on
2processor ASICs implemented
02 / Expertise
What I actually build
From floorplan to tapeout, plus the research that makes circuits survive radiation.
Timing Closure & STA
Multi-mode multi-corner (MMMC) timing analysis and closure with PrimeTime and Tempus. Setup/hold fixing, ECOs and congestion-aware optimization.
Physical Verification
DRC, LVS, antenna and density checks with industry tools, delivering signoff-quality layouts in advanced technologies.
Fault-Tolerant Design
Radiation-resilient combinational circuits and robust standard cell libraries for reliability in harsh environments.
RISC-V & ASIC Research
Founder and technical lead of OSIRIS: RISC-V microarchitecture, RTL design and ASIC implementation with open-source flows (SkyWater 130 nm / 65 nm).
Automation & Scripting
Flow automation and tool integration in TCL and Python to boost productivity and enable scalable design methodologies.
03 / Toolbox
Core tools & technologies
The flows and languages I use day to day.
Implementation & signoff
Methodology
Languages & tools
Spoken
04 / Research
All publications
Latest publications
Radiation effects and variability in combinational cells.
SET Mitigation Techniques for Full Adders at 7 nm
Mirror, Hybrid, TGA and TFA full adders under nominal and near-threshold operation, hardened with decoupling cells and transistor sizing.
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SET Mitigation for Mirror and Hybrid Full Adders
Decoupling cells and transistor sizing applied to two full adder topologies in 7 nm FinFET.
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Process Variability in XOR-based Full Adders
Delay and energy of traditional and XOR-based full adders under process variability, at nominal and near-threshold voltage.
Read summary →
05 / Projects
All projects
Selected projects
Processors taken to silicon, and a few side quests.
06 / Contact
Let’s talk silicon
Open to conversations about physical design, timing closure, reliability research and RISC-V.