Oliveira
Physical Design Engineer & STA Engineer
Intro
Physical Design Engineer & Researcher.
I hold a Bachelor of Science in Computer Science from the Federal University of Santa Catarina (UFSC) and am currently completing my Master of Science in Computer Science at UFSC. Since 2018, I have conducted research in microelectronics and nanotechnology, focusing on mitigating variability and radiation-induced circuit failures. My expertise includes integrated circuit physical design and fault-tolerant combinational circuit design, with hands-on experience across the full RTL-to-GDSII flow using industry-standard EDA tools. I also work on radiation-hardened standard cell libraries and low-power RISC-V ASIC solutions. I have extensive experience in advanced-node ASIC implementation (180nm to 12nm), electrical characterization, and timing-driven design closure. I have authored publications in international journals and conferences in the fields of digital design and fault tolerance. I am the founder of OSIRIS, a research group focused on RISC-V microarchitecture development, and creator of VLSI Brasil, a blog dedicated to semiconductor knowledge sharing in Portuguese.
Expertise
What I actually build.
01
ASIC Physical Design
End-to-end backend implementation from synthesized netlist to GDSII. Experience across advanced nodes (180nm to 12nm), including floorplanning, placement, CTS, routing, and physical optimization.
02
Timing Closure & STA
Multi-mode multi-corner (MMMC) timing analysis and closure using PrimeTime and Tempus. Setup/hold fixing, ECO implementation, and congestion-aware optimization.
03
Physical Verification
DRC, LVS, antenna, and density checks using industry tools. Strong experience ensuring signoff-quality layouts in advanced technologies.
04
Fault-Tolerant Design
Design of radiation-resilient combinational circuits and development of robust standard cell libraries targeting reliability in harsh environments.
05
RISC-V & ASIC Research
Founder and technical lead of OSIRIS. Work includes RISC-V microarchitecture development, RTL design, and ASIC implementation using open-source flows (SkyWater 130nm / 65nm).
06
Automation & Scripting
Flow automation and tool integration using TCL and Python to improve productivity and enable scalable design methodologies.
Skills
Core tools & technologies.