Physical Design Engineer & STA Engineer
What I am all about.
Physical Design Engineer with experience in end-to-end ASIC implementation from netlist to GDSII across advanced technology nodes (130nm, 22nm to 7nm). Strong background in timing-driven design closure, multi-mode multi-corner (MMMC) analysis, and physical verification.
Skilled in floorplanning, placement, clock tree synthesis, routing, and signal integrity analysis, with hands-on experience in timing closure, ECO implementation, and congestion optimization. Experienced in automating design flows using TCL and Python.
Founder and technical lead of a RISC-V initiative focused on microarchitecture development and ASIC implementation using open-source EDA flows. Research experience includes radiation effects, fault-tolerant design, and circuit-level reliability analysis in advanced FinFET technologies.
Batman would be jealous.
Definition and validation of timing constraints for complex ASIC designs, including clocks, exceptions, and IO constraints, ensuring accurate STA and timing closure across MMMC scenarios.
Low-power design implementation using UPF, including power domains, isolation strategies, level shifters, and power intent verification for energy-efficient ASIC designs.
Development of efficient floorplans including macro placement, power grid design, and congestion-aware partitioning to enable optimal performance, power, and routability.
Full place-and-route implementation from synthesized netlist to tapeout, including placement, CTS, routing, and physical optimization using industry-standard EDA tools.
Static Timing Analysis and timing closure using MMMC methodologies, including setup/hold fixing, ECO implementation, and timing-driven optimization.
Physical verification and signoff using DRC, LVS, antenna, and density checks to ensure manufacturability and compliance with advanced-node design rules.