SDC
Definition and validation of timing constraints for complex ASICs (clocks, exceptions, IO) for accurate STA and closure across MMMC scenarios.
Experience
Physical Design & STA Engineer
End-to-end ASIC implementation from netlist to GDSII across 130 nm and 22 nm to 7 nm, with a strong background in timing-driven closure, MMMC analysis and physical verification.
Skilled in floorplanning, placement, clock tree synthesis, routing and signal integrity analysis.
Hands-on experience with timing closure, ECO implementation and congestion optimization, and with automating design flows in TCL and Python.
Founder and technical lead of a RISC-V initiative focused on microarchitecture development and ASIC implementation with open-source EDA flows. Research experience includes radiation effects, fault-tolerant design and circuit-level reliability analysis in advanced FinFET technologies.
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Now
Physical Design & STA Engineer
Netlist-to-GDSII implementation and signoff timing in advanced nodes.
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Founder
OSIRIS · VLSI Brasil
RISC-V research group and a Portuguese-language semiconductor blog.
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2018 – present
VLSI researcher, UFSC
Radiation effects and variability in FinFET combinational cells.
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Education
B.Sc. & M.Sc. Computer Science
Federal University of Santa Catarina (UFSC).
Core competencies
Across the backend flow
The pieces of the flow I own, from constraints to signoff.
UPF
Low-power implementation with UPF: power domains, isolation strategies, level shifters and power-intent verification.
Floorplanning
Macro placement, power grid design and congestion-aware partitioning for optimal performance, power and routability.
Place & Route
Full PnR from synthesized netlist to tapeout, including placement, CTS, routing and physical optimization.
STA
Static timing analysis and closure using MMMC methodologies: setup/hold fixing, ECO implementation and timing-driven optimization.
DRC / LVS
Physical verification and signoff with DRC, LVS, antenna and density checks for advanced-node manufacturability.
Toolbox
Tools & technologies
The flows and languages I use day to day.